線路板設計(英文)(pdf 6頁)

In order to guarantee better performance from highspeed
digital integrated circuits (ICs), manufacturers
are tightening power supply noise margins. With lower
power supply noise margins, the designer needs to pay
closer attention to local bypass capacitor selection.
As bus speeds increase and switching times decrease,
proper selection of local bypass capacitors for highspeed
digital ICs is becoming increasingly complex.
With wider parts becoming prevalent in cache subsystems,
the amount of current required from the
bypass capacitor to decouple noise from the current
transients switching across the power bus is increasing.
At the same time that the current transients become
larger, the need to choose smaller capacitance values is
becoming more important. Smaller capacitance values
offer lower series inductance.
The role of the bypass capacitor is to decouple the
power supply bus from the IC. Figure 1 shows the
equivalent circuit of a decoupling loop. The objective is
to eliminate the effects of the power bus inductance
and resistance (R1, Rg2, L2, Lg2 in Figure 1) so that
transient currents flowing across the power bus do not
cause excessive noise at the power and ground pins of……
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