三星的S3C44B0X中文數據手冊.doc47

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介紹

三星的S3C44B0X 16/32位RISC處理器被設計來為手持設備等提供一個低成本高性能的方案。

S3C44B0X提供以下配置：2.5VARM7TDMI內核帶有8Kcache ;可選的internal SRAM;LCD Controller(最大支持256色STN，使用LCD專用DMA)；2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO；2-ch general DMAs / 2-ch peripheral DMAs with external request pins；External memory controller (chip select logic, FP/ EDO/SDRAM controller)；5-ch PWM timers & 1-ch internal timer；Watch Dog Timer；71 general purpose I/O ports / 8-ch external interrupt source；RTC with calendar function；8-ch 10-bit ADC；1-ch multi-master IIC-BUS controller；1-ch IIS-BUS controller；Sync. SIO interface and On-chip clock generator with PLL.。

S3C44B0X采用一種新的三星ARM CPU嵌入總線結構-SAMBA2，最大達66MHZ。

電源管理支持：Normal, Slow, Idle, and Stop mode。

係統管理功能：

1 Little/Big endian support.

2 Address space: 32Mbytes per each bank. (Total 256Mbyte)

3Supports programmable 8/16/32-bit data bus width for each bank.

4 Fixed bank start address and programmable bank size for 7 banks.

5 .8 memory banks.

- 6 memory banks for ROM, SRAM etc.

- 2 memory banks for ROM/SRAM/DRAM(Fast Page, EDO, and Synchronous DRAM)

6.Fully Programmable access cycles for all memory banks.

7Supports external wait signal to expend the bus cycle.

8.Supports self-refresh mode in DRAM/SDRAM for power-down.

9.Supports asymmetric/symmetric address of DRAM.

Cache和內部存儲器功能:

·4-way set associative ID(Unified)-cache with 8Kbyte.

·The 0/4/8 Kbytes internal SRAM using unused cache memory.

·Pseudo LRU(Least Recently Used) Replace Algorithm.

·Write through policy to maintain the coherence between main memory and cache content.

·Write buffer with four depth.

·Request data first fill technique when cache miss occurs.

時鍾和電源管理

·Low power

·The on-chip PLL makes the clock for operating MCU at maximum 66MHz.

·Clock can be fed selectively to each function block by software.

·Power mode: Normal, Slow, Idle and Stop mode.

Normal mode: Normal operating mode.

Slow mode: Low frequency clock without PLL

Idle mode: Stop the clock for only CPU

Stop mode: All clocks are stopped

·Wake up by EINT[7:0] or RTC alarm interrupt from

idlemode.

中斷控製器

·30 Interrupt sources( Watch-dog timer, 6 Timer, 6 UART, 8 External interrupts, 4 DMA , 2 RTC, 1 ADC, 1 IIC, 1 SIO )

·Vectored IRQ interrupt mode to reduce interruptlatency.

·Level/edge mode on the external interrupt sources

·Programmable polarity of edge and level

·Supports FIQ (Fast Interrupt request) for very urgent interrupt request

定時器功能

·5-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based

operation

·Programmable duty cycle, frequency, and polarity

·Dead-zone generation.

·Supports external clock source.

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